1. Field of the Invention
The invention generally relates to a electrostatic discharge (ESD) design system and method of use and, more particularly, to an automated computer aided design (CAD) system and method of use for design, verification and checking of ESD circuits for a given application.
2. Background Description
As electronic components become smaller and smaller along with the internal structures in integrated circuits, it is becoming easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity, even at levels which can neither be seen nor felt. This is typically referred to as electrostatic discharge (ESD), in which the transfer of an electrostatic charge occurs between bodies at different electrostatic potentials (voltages) caused by direct contact or induced by an electrostatic field.
The discharge of static electricity, or ESD, has become a critical problem for the electronics industry. Device failures are not always immediately catastrophic, but often the device is weakened thus less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components, with various considerations necessary for ESD protection circuits.
For example, ESD protection circuits for input nodes must support quality dc, ac, and RF model capability in order to co-design ESD circuits for analog and RF circuits. With the growth of the high-speed data rate transmission, optical interconnect, wireless and wired marketplaces, the breadth of applications and requirements is broad. Each type of application space has a wide range of power supply conditions, number of independent power domains, and circuit performance objectives. As a result, an ESD design system which has dc and RF characterized models, design flexibility, automation, ESD characterization, and satisfies digital, analog and RF circuits is required to design and co-synthesize ESD needs of mixed signal RF technology.
Much effort has been expended by industry to protect electronic devices from ESD damage. Traditionally, ESD designs are custom designed using graphical systems. ESD ground rules and structures are typically built into the designs requiring a custom layout. This has lead to custom design for digital products such as, for example, DRAMs, SRAMs, microprocessors, ASIC development and foundry technologies. This design practice does not allow for the flexibility needed for RF applications.
A difficulty in the design of RF ESD solutions is that traditionally, specific designs are fixed in size in order to achieve verifiable ESD results for a technology. The difficulty with analog and RF technology is that a wide range of circuit applications exists where one ESD size structure is not suitable due to loading of the circuit. A second issue is that the co-synthesis of the circuits must be done to properly evaluate the RF performance objectives. RF characterization of the network that is flexible with the device size is important for the evaluation of the tradeoffs of RF performance and ESD.
A third issue for RF mixed signal designs, there are analog and digital circuits. In these environments, there are some products which primarily use digital CMOS circuits and some which are bipolar dominated. In this environment, some applications prefer CMOS-based ESD networks, and others are motivated to use Bipolar-based ESD networks.
Additional difficulties are encountered from the different views of an ESD circuit (e.g., symbol, circuit schematic and graphical representations) and the mapping from the graphical to circuit representations, circuit schematic representation to the graphical representation in the environment of a variable ESD circuit sizes. New solutions are developed to provide a methodology and structure to allow flexibility of mapping between representations in the environment of these different size elements.
In this environment, the verification and checking is necessary to evaluate ESD chip robustness. This may include, for example, the verification of the pads, the ESD input circuit, the ESD power clamp circuit, ESD rail-to-rail circuits, interconnects between the input pad and the ESD circuits, interconnects between power pads and the ESD power rails, the interconnects between two power rails for rail-to-rail ESD networks, the verification of ESD rail-to-rail type designs between functional blocks, verification of type of ESD networks on analog, digital and RF circuits, verification of the correct ESD network for a given chip circuit, verification of the critical size of the interconnects, verification of the size and adequacy of the ESD network are all important to provide ESD protection of RF BiCMOS, RF BiCMOS Silicon Germanium (hereinafter referred generally as BiCMOS) and RF CMOS applications.